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ltc3725 1 3725fa features descriptio u applicatio s u typical applicatio u isolated 48v telecommunication systems internet servers and routers distributed power step-down converters automotive and heavy equipment high speed gate driver for forward converter on-chip rectifier and self-starting architecture eliminates need for separate gate drive bias supply wide input voltage supply range: 9v and up linear regulator controller for fast start-up precision uvlo with adjustable hysteresis overcurrent protection volt-second limit prevents transformer core saturation voltage feedforward for fast transient response available in 10-lead msop package single-switch forward controller and gate driver the ltc 3725 is a controller for a single-switch forward converter and includes an on-chip gate driver. for secondary-side control, combine the ltc3725 with the ltc3706 polyphase secondary-side synchronous forward controller to create a complete forward converter using a minimum of discrete parts. a proprietary scheme is used to multiplex gate drive signals across the isolation barrier through a tiny pulse transformer. the on-chip rectifier and the same pulse transformer provide gate drive bias power. alternatively, the ltc3725 can be used as a standalone voltage mode controller in a primary-side control architec- ture with optoisolator feedback. voltage feedforward pro- vides excellent line regulation and transient response. 36v-72v to 3.3v/30a isolated single-switch forward converter , lt, ltc and ltm are registered trademarks of linear technology corporation. polyphase is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. patent pending fb/in + 1 f 100v 2 v in + 36v to 72v v in 2.2nf 200v 10 f 100 f 6.3v 2 220 f 6.3v v out + 3.3v 30a v out 47nf 470pf 33nf b0540w si7450dp 33nf 15k 1 f 0.1 f 0.030 ? 1w 1 f 2.2 f 0.0012 ? 1w hat2165 2 hat2165 2 l1 0.85 h t2 162k l1: pulse pa1294.910 t1: pulse pa0815 t2: pulse pa0297 5.1k 3.3k 100k 2.74k 604 ? 3725 ta01 1.2 ? 1/4w 100k fs/in v cc uvlo ssflt i s gate ltc3725 ndrv gnd pgnd v slmt 365k fdc2512 t1 pt + fg sw i s i s + sg v in v cc mode ndrv gnd pgnd run/ss slp regsd fs/sync i th phase fcx491a pt fb ltc3706 +
ltc3725 2 3725fa power supply (v cc ) ................................... 0.3v to 15v external nmos drive (ndrv) .................... 0.3v to 20v ndrv to v cc ........................................................... 0.3v to 5v soft-start fault, feedback, frequency set, transformer inputs (ssflt, fb/in + , fs/in ) .................. 0.3v to 15v all other pins (v slmt , i s , uvlo) ................. 0.3v to 5v peak output current <1 s (gate) ............................. 2a operating ambient temperature range .. 40 c to 85 c operating junction temperature (note 2) ............ 125 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 125 c, ja = 45 c/w, jc = 10 c/w exposed pad (pin 11) is gnd, must be soldered to pcb ltc3725emse ltc3725imse absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 12v, gnd = pgnd = 0v, t a = 25 c, unless otherwise noted. mse part marking 1 2 3 4 5 uvlo ssflt ndrv fb/in + fs/in 10 9 8 7 6 i s v slmt v cc gate pgnd top view 11 mse package 10-lead plastic msop ltbsv ltbsw order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts specified with wider operating temperature ranges. symbol parameter conditions min typ max units v cc supply, linear regulator and trickle charger shunt regulator v ccop operating voltage range 7 12 15 v v cclr output voltage linear regulator in operation 8 v i ndrv current into ndrv pin linear regulator in operation 0.1 1 ma t r(vcc) rise time of v cc linear regulator charging (0.5v to 7.5v) 45 s i ndrvto linear regulator time out current threshold primary-side operation 0.27 ma i cc supply current v uvlo = 1.5v, linear regulator in 1.4 2.1 ma operation (note 3) i ccm maximum supply current v uvlo = 1.5v, trickle charger in operation, 1.7 2.5 ma v cc = 13.2v (note 3) v ccsr maximum supply voltage trickle charger shunt regulator 14.25 15 v i ccsr minimum current into ndrv/v cc trickle charger shunt regulator, v cc = 15v 10 ma (note 3) internal undervoltage v ccuv internal undervoltage threshold v cc rising 5.3 v v cc falling 4.7 v gate drive undervoltage v gduv gate drive undervoltage threshold v cc rising (linear regulator) 7.2 7.4 7.7 v v cc rising (trickle charger) 13.1 13.4 14 v v cc falling 6.8 7.0 7.2 v undervoltage lockout (uvlo) v uvlor undervoltage lockout threshold rising rising 1.220 1.242 1.280 v v uvlof undervoltage lockout threshold falling falling 1.205 1.226 1.265 v
ltc3725 3 3725fa the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 12v, gnd = pgnd = 0v, t a = 25 c, unless otherwise noted. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: operating junction temperature t j (in c) is calculated from the ambient temperature t a and the average power dissipation pd (in watts) by the formula: t j = t a + ja ?pd. refer to the applications information section for details. note 3: i cc is the sum of current into ndrv and v cc . note 4: the ltc3725emse is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the ?0 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3725imse is guaranteed and tested over the 40 c to 85 c operating temperature range. symbol parameter conditions min typ max units i huvlo hysteresis current v uvlo = 1v 4.2 4.9 5.6 a v uvloop voltage feedforward operating range primary-side control v uvlof(min) 3.75 v gate driver (gate) r os output pull-down resistance i out = 100ma 1.9 ? v oh high output voltage i out = ?00ma 11 v i pu peak pull-up current 1.7 a t r output rise time 10% to 90%, c out = 4.7nf 40 ns t f output fall time 10% to 90%, c out = 4.7nf 70 ns rectifier i rect maximum rectifier dc output current 25 ma oscillator f osc(p) oscillator frequency primary-side control, r fs(p) = 100k ? 200 khz primary-side control, r fs(p) = 25k ? 700 khz primary-side control, r fs(p) = 300k ? 70 khz ? f rfs(p) oscillator resistor set accuracy primary-side control 25k < r fset < 300k 15 % f osc(s) oscillator frequency secondary-side control (during start-up), 300 khz r fs(s) = 100k ? soft-start/fault (ssflt) i ss(c) soft-start charge current primary-side control, v ssflt = 2v 5.2 a secondary-side control, v uvlo = 1.3v, 4 a v ssflt = 2v secondary-side control, v uvlo = 3.75v, 1.6 a v ssflt = 2v v lrto linear regulator time out-threshold 3.9 v v flth fault output high v cc = 8v 6.7 v i ss(d) soft-start discharge current timing out after fault, v ssflt = 2v 1 a current sense input (i s ) v is(max) overcurrent threshold 300 mv volt second limit (v slmt ) v vsl(max) volt-second limit threshold 1.26 v i vslmt(max) maximum volt-second limit resistor current 0.25 ma optoisolator bias current v opto open circuit optoisolator voltage primary-side control i fb = 0v 3.3 v i opto optoisolator bias current primary-side control v fb = 2.5v 0.5 ma primary-side control v fb = 0v 1.6 ma
ltc3725 4 3725fa supply current vs v cc uvlo voltage threshold vs temperature uvlo hysteresis current vs temperature oscillator frequency f osc vs r fset oscillator frequency vs temperature shunt regulator current i cc vs v cc shunt regulator current vs temperature v gduv vs temperature typical perfor a ce characteristics uw optoisolator bias v fb/in + vs i fb/in + v cc (v) 0 current (ma) 1.0 1.5 15 3725 g01 0.5 0 10 5 2.0 trickle charger linear regulator temperature ( c) ?0 uvlo threshold (v) 1.240 1.235 1.230 1.225 100 3725 g02 1.220 40 60 80 0 ?0 20 ?0 1.245 v uvlof v uvlor temperature ( c) ?0 i huvlo ( a) 5.00 4.95 4.90 4.85 100 3725 g03 4.80 40 60 80 0 ?0 20 ?0 5.05 r fset (k ? ) 0 f osc (khz) 300 200 100 400 300 200 100 3725 g04 0 800 700 400 500 600 secondary-side control primary-side control temperature ( c) ?0 oscillator frequency f osc(p) (khz) 202 201 200 199 100 3725 g05 197 198 40 60 80 0 ?0 20 ?0 203 primary-side control r fs(p) = 100k ? v cc (v) 14.00 i cc (ma) 9 6 3 15.00 14.75 14.50 14.25 3725 g06 0 18 12 15 temperature ( c) ?0 i ccsr (ma) 100 3725 g07 15 16 17 18 19 40 60 80 0 ?0 20 ?0 25 24 23 22 21 20 temperature ( c) ?0 v gduv (v) 100 3725 g08 6 7 8 40 60 80 0 ?0 20 ?0 14 13 12 11 10 9 v cc rising (trickle charger) v cc rising (linear regulator) v cc falling (both) ? fb/in + (ma) 0 v fb/in + (v) 1.5 1.0 0.5 2.0 1.5 1.0 0.5 3725 g09 0 3.5 2.0 2.5 3.0
ltc3725 5 3725fa typical perfor a ce characteristics uw gate drive pull-down resistance vs temperature gate drive peak pull-up current vs temperature linear regulator start-up gate drive encoding fault operation temperature ( c) ?0 gate drive resistance r os ( ? ) 2.25 2.00 1.75 100 3725 g10 1.50 40 60 80 0 ?0 20 ?0 2.50 temperature ( c) ?0 i pu (a) 1.9 1.8 1.7 1.6 100 3725 g11 1.5 40 60 80 0 ?0 20 ?0 2.0 5v/div 25 s/div 3725 g12 v in ndrv v cc 10v/div 1 s/div 3705 g13 gate fb/in fs/in 2v/div 10v/div 40ms/div 3725 g14 gate ssflt
ltc3725 6 3725fa uu u pi fu ctio s uvlo (pin 1): undervoltage lockout. connect to a resis- tive voltage divider to monitor input voltage v in . enables converter operation for v uvlo > 1.242v. hysteresis is a fixed 16mv hysteresis voltage with a 4.9 a hysteresis current that combines with the thevenin resistance of the divider to set the total uvlo hysteresis voltage. this input also senses v in for voltage feedforward. finally, this pin can be used for external run/stop control. ssflt (pin 2): combination soft-start and fault indica- tor. a capacitor to gnd sets the duty cycle ramp-up rate during start-up. to indicate a fault, the ssflt pin is momentarily pulled up to within 1.3v of v cc . ndrv (pin 3): drive for the external nmos linear regu- lator. connect to the gate of the nmos and connect a pull up resistor to the input voltage (v in ). optionally, to create a trickle charger omit the nmos device and connect ndrv to v cc . fb/in + (pin 4): this pin has several functions. one wind- ing of a pulse transformer is connected to the fb/in + and fs/in pins. the other pulse transformer winding is con- nected to the ltc3706. the ltc3725 automatically de- tects when the ltc3706 applies a pulse-encoded signal to the fb/in + and fs/in pins and decodes duty cycle infor- mation for control of the primary-side gate drive (see operation below). in secondary-side control, primary- side gate drive bias power is also extracted from the fb/in + and fs/in pins using an on-chip full-wave rectifier. for primary-side control connect this pin to an optoisolator for feedback control of converter output voltage using an internal optoisolator biasing network. fs/in (pin 5): this pin has several functions. place a resistor from this pin to gnd to set the oscillator fre- quency. for secondary-side control with the ltc3706, connect one winding of the pulse transformer for opera- tion as described for the fb/in + pin above. pgnd (pin 6): supply return for the bottom gate driver and the on-chip bridge rectifier. gate (pin 7): gate drive. connect to the gate of the external mosfet. v cc (pin 8): main v cc power for all driver and control circuitry. v slmt (pin 9): volt-second limit. form an r-c integrator by connecting a resistor from v in to v slmt and a capacitor from v slmt to ground. the gate drive is turned off when the voltage on the v slmt pin exceeds 1.26v. i s (pin 10): input to the overcurrent comparator. connect to the positive terminal of a current-sense resistor in series with the source of the ground-referenced bottom mosfet. gnd (pin 11): signal ground.
ltc3725 7 3725fa block diagra w + + + + + + + + 7.4v/7v linear regulator 13.4v/7v trickle charger + 5.3v/4.7v 14.25v 5v soft-start fault regulator + v 0.27ma line off time 4.9 a 0.66 v ff 1.242v 1.226v uvint uvgd 300mv 3 2 10 1 11 ndrv ssflt uvlo gnd (pad) fb/in + fs/in frequency set opto bias rectifier pwm receiver condition sw det in + in v cc shunt regulator is 7 gate 8 v cc 6 pgnd v cc pgnd trickle charge 8v 0.6v 400mv i ndrv uvvin 5v pwm primary control drive logic 9 v slmt oscillator 2v n/c 0v v p-p i osc primary side control pwm secondary control secondary side control 3.3v 4 5 clock ramp v p-p switch on 1.26v oc 3725 bd sw det
ltc3725 8 3725fa mode setting the ltc3725 is a controller and gate driver designed for use in a single-switch forward converter. when used in conjunction with the ltc3706 polyphase secondary- side synchronous forward controller, it forms a complete forward converter with secondary-side regulation, gal- vanic isolation between input and output, and synchro- nous rectification. in this mode, upon start-up, the fb/ in + and fs/in pins are effectively shorted by one winding of the pulse transformer. the ltc3725 detects this short circuit to determine that it is in secondary-side control mode. operation in this mode is confirmed when the ltc3706 begins switching the pulse transformer. alternately, the ltc3725 can be used as a standalone primary-side controller. in this case, the fb/in + and fs/in pins operate independently. the fb/in + pin is connected to the collector of an optoisolator to provide feedback and the fs/in pin is connected to the frequency set resistor. gate drive encoding in secondary-side control with the ltc3706, after a start- up sequence, the ltc3706 transmits multiplexed pwm information through a pulse transformer to the fb/in + and fs/in inputs of the ltc3725. in the ltc3725, the pwm receiver extracts the duty cycle and uses it to control the gate driver. figure 1 shows that the ltc3706 drives the pulse trans- former in a complementary fashion, with a duty cycle of approximately 75%. at the appropriate time during the posi- tive half cycle, the ltc3706 applies a short (150ns) zero- voltage pulse across the pulse transformer, indicating the end of the ?n?time. although this scheme allows the trans- mission of 0% to 75% duty cycle, it is necessary to estab- lish a minimum controllable ?n?time of approximately 100ns. this ensures that 0% duty cycle can be reliably dis- tinguished from 75% duty cycle. on-chip rectifier simultaneously with duty-cycle decoding, and through the same pulse transformer, the wave generated by the ltc3706 provides primary-side v cc gate drive bias power by way of the ltc3725? on-chip full-wave bridge rectifier. no auxiliary bias supply is necessary and forward con- verter design and circuitry are considerably simplified. external series pass linear regulator the ltc3725 features an external series pass linear regu- lator that eliminates the long start-up time associated with the conventional trickle charger. the drain of an external nmos is connected to the input voltage and the source is connected to v cc . the gate of the nmos is connected to ndrv. to power the gate, an external pull-up resistor is connected from the input voltage to ndrv. the nmos must be a standard 3v threshold type (i.e. not logic level). an on-chip circuit manages the start up and operation of the linear regulator. it takes approximately 45 s for the linear regulator to charge v cc to its target value of 8v (unless limited by a slower rise of v in ). the ltc3725 begins operating the gate drives when v cc reaches 7.4v. often, the thermal rating of the nmos prevents it from operating continuously, and the ltc3725 ?imes out?the linear regulator to prevent overheating. this is accom- plished using the capacitor connected to the ssflt pin as described subsequently. trickle charger shunt regulator alternately, a trickle charger can be implemented by eliminating the external nmos and connecting ndrv to v cc and using the pull-up resistor to charge v cc . to allow extra headroom for starting, the ltc3725 detects this mode and increases the threshold for starting the gate drives to 13.4v. an internal shunt regulator limits the voltage on the trickle charger to 15v. operatio u figure 1. gate drive multiplexing scheme duty cycle = 15% duty cycle = 0% 150ns 150ns 150ns 3725 f01 1 clk per 1 clk per +7v ?v v pt1 + ?v pt1
ltc3725 9 3725fa self-starting architecture the ltc3725 is combined with the ltc3706 to form a complete self-starting dc isolated power supply. when power is first applied, and when v cc for the ltc3725 is above the appropriate threshold, the ltc3725 begins open-loop operation using its own internal oscillator. power is supplied to the secondary by switching the gate driver with a gradually increasing duty cycle as controlled by the rate of rise of the voltage on the ssflt pin. a peak detector power supply for the ltc3706 allows it to begin operation even for small duty cycles. once adequate voltage is available for the ltc3706, it provides duty cycle information and gate drive bias power using the pulse transformer as shown in figure 1. the ltc3725 detects the appearance of this signal and transfers control of the gate drivers to the ltc3706. simultaneously, the ltc3725 also enables the on-chip rectifier and turns off the linear regulator. alternately, when the ltc3725 is used as a standalone primary-side controller, the gradually increasing duty cycle powers up a secondary-side reference and optoisolator and feedback is accomplished when the output of the optoisolator begins pulling down in the fb/in + pin. soft-start and fault these two functions are implemented using the ssflt pin. (this pin is also used for linear regulator timeout as described in the following section.) initiating soft-start requires that: 1) the gate drive undervoltage (uvgd) goes low meaning that adequate voltage is available on the v cc pin (7.4v for the linear regulator or 13.4v for the trickle charger) and 2) the input undervoltage (uvv in ) goes low meaning that the voltage on the uvlo pin has reached the 1.242v rising threshold. during soft-start, the ltc3725 gradually charges the soft- start capacitor to ramp up the converter duty cycle. soft- start is over when the voltage on the ssflt pin reaches 2.8v. in normal operation, at some point before this, the ltc3725 makes a transition to controlling duty cycle using closed- loop regulation of the converter output voltage. the ssflt pin is also used to indicate a fault. the ltc3725 recognizes faults from four origins: 1) an overcurrent fault caused by the current sense voltage on the is pin exceed- ing the 300mv overcurrent threshold, 2) an input undervoltage fault caused by the uvlo pin falling below the 1.226v falling threshold, 3) a gate drive undervoltage fault caused by the voltage on the v cc pin falling below the 7v threshold, or 4) loss of the gate drive encoding signal from the ltc3706. upon sensing a fault, the ltc3725 immediately turns off the gate drive and indicates a fault by quickly pulling the voltage on the ssflt pin to within 1.3v of the voltage on the v cc pin. after indicating the fault, the ltc3725 quickly ramps down the voltage on the ssflt pin to approxi- mately 2.8v. then, to allow complete discharge of the secondary-side circuit, the ltc3725 slowly ramps down the voltage on the ssflt pin to about 200mv. the ltc3725 then attempts a restart. linear regulator timeout the thermal rating of the linear regulator? external nmos often cannot allow it to indefinitely supply bias current to the primary-side gate drives. the ltc3725 has a linear regulator timeout mechanism that also uses the ssflt capacitor. as described in the prior section, soft-start is over once the voltage on the ssflt pin reaches 2.8v. however, the ssflt capacitor continues to charge and the linear regu- lator is turned off when the voltage on the ssflt pin reaches 3.9v. the ?pplications information?section de- scribes linear regulator timeout in more detail. volt-second limit the volt-second limit ensures that the power transformer core does not saturate for any combination of duty cycle and input voltage. the input of an r-c integrator is connected to v in and its output is connected to the v slmt pin. while the gate drive is ?ff,?the ltc3725 grounds the v slmt pin. when the gate drive is turned ?n?the v slmt pin is released and the capacitor is allowed to charge in proportion to v in . if the capacitor voltage on the v slmt pin operatio u
ltc3725 10 3725fa exceeds 1.26v the gate drive is immediately turned ?ff. note that this is not considered a fault condition and the ltc3725 can run indefinitely with the switch duty cycle being determined by the volt-second limit circuit. the duty cycle is always limited to 75% to ensure that the power transformer flux always has time to reset before the start of the next cycle. in an alternate application, the volt-second limit can be used for open-loop regulation of the output against changes in v in . current limit current limit for the ltc3725 is principally a safety feature to protect the converter and is not part of a control function. the current that flows in series through the transformer primary and the switch is sensed by a resistor connected between the source of the switch and gnd. if the voltage across this resistor exceeds 300mv, the ltc3725 initiates a fault. voltage feedforward the ltc3725 uses voltage feedforward to properly modu- late the duty cycle as a function of the input voltage. for secondary-side control with the ltc3706, voltage feedforward is used during start-up only. the duty cycle during start up is determined by comparison of the voltage on the ssflt pin to a 75% duty cycle triangle wave with an amplitude of 2v. to implement voltage feedforward, the charging current for the soft-start capacitor is reduced in proportion to the input voltage. as a result, the initial rate of rise of the converter output voltage is held approxi- mately constant regardless of the input voltage. at some point during start-up, the ltc3706 begins to switch the pulse transformer and take over the soft-start. for operation with standalone primary-side control and optoisolator feedback, voltage feedforward is used during both start-up and normal operation. the duty cycle is determined by using a 75% duty cycle triangle wave with an amplitude equal to 66% of the voltage on the uvlo pin which is, in turn, proportional to v in . the charging current for the soft-start capacitor is a constant 5.2 a. during soft-start, the duty cycle is determined by comparing the voltage on the ssflt pin to the triangle wave. soft-start is concluded when the voltage on the ssflt pin exceeds the voltage on the fb/in + pin. after the conclusion of soft- start, the duty cycle is determined by comparison of the voltage on the fb/in + pin to the triangle wave. optoisolator bias when the ltc3725 is used in standalone primary-side mode, feedback is provided by an optoisolator connected to the fb/in + pin. the ltc3725 has a built optoisolator bias circuit which eliminates the need for external components. operatio u
ltc3725 11 3725fa note that a trickle charger usually requires a large capaci- tor to provide holdup for the v cc pin while the converter attempts to start. the linear regulator in the ltc3725 can both charge the capacitor connected to the v cc pin and provide primary-side gate-drive bias current. therefore, with the linear regulator, the capacitor need only be large enough to cope with the ripple current from driving the gate of the primary fet and holdup need not be considered. the external nmos for the linear regulator should be a standard 3v threshold type (i.e. not a logic level thresh- old). the rate of charge of v cc from 0v to 8v is controlled by the ltc3725 to be approximately 45 s regardless of the size of the capacitor connected to the v cc pin. the charging current for this capacitor is approximately: i v s c c = 8 45 the safe operating area (soa) for the external nmos should be chosen so that capacitor charging does not damage the nmos. excessive values of capacitor are unnecessary and should be avoided. start-up considerations when used in a self-starting converter with the ltc3706, the ltc3725 initially begins the soft-start of the converter in an open-loop fashion. after bias is obtained on the secondary side, the ltc3706 assumes control and com- pletes the soft-start interval. in order to ensure that control is properly transferred from the ltc3725 (primary-side) to the ltc3706 (secondary-side), it is necessary to limit the rate of rise on the primary-side soft-start ramp so that the ltc3706 has adequate time to wake up and assume control before the output voltage gets too high. this condition is satisfied for many applications if the following relationship is maintained: c ss,sec c ss_pri applicatio s i for atio wu u u figure 2. resistive voltage divider for uvlo and optional run/stop control uvlo the uvlo pin is connected to a resistive voltage divider connected to v in as shown in figure 2. the voltage threshold on the uvlo pin for v in rising is 1.242v. to introduce hysteresis, the ltc3725 draws 4.9 a from the uvlo pin when v in is rising. the hysteresis is therefore user adjustable and depends on the value of r1. the uvlo threshold for v in rising is: vv rr r ra in uvlo rising (, ) (. ) (. ) = + + 1 242 12 2 149 the ltc3725 also has 16mv of voltage hysteresis on the uvlo pin so that the uvlo threshold for v in falling is: vv rr r in uvlo falling (, ) (. ) = + 1 226 12 2 to implement external run/stop control, connect a small nmos to the uvlo pin as shown in figure 2. turning the nmos on grounds the uvlo pin and prevents the ltc3725 from running. r1 r2 v in run/stop control (optional) uvlo gnd ltc3725 3725 f02 linear regulator the linear regulator eliminates the long start-up times associated with a conventional trickle charger by using an external nmos to quickly charge the capacitor connected to the v cc pin.
ltc3725 12 3725fa however, care should be taken to ensure that soft-start transfer from primary-side to secondary-side is com- pleted well before the output voltage reaches its target value. a good design goal is to have the transfer completed when the output voltage is less than one-half of its target value. note that the fastest output voltage rise time during primary-side soft-start mode occurs with minimum load current. the open-loop start-up frequency on the ltc3725 is set by placing a resistor r fs(s) from the fs/in pin to gnd. although the exact start-up frequency on the primary side is not critical, it is generally a good practice to set it approximately equal to the operating frequency on the secondary side. in this mode the start-up frequency of the ltc3725 is approximately: f r pri fs s = + 34 10 10 000 9 , () in the event that the ltc3706 fails to start up properly and assume control of switching, there are several fail-safe mechanisms to help avoid overvoltage conditions. first, the ltc3725 implements a volt-second clamp that may be used to keep the primary-side duty cycle at a level that does not produce an excessive output voltage. second, the timeout of the linear regulator (described in the follow- ing section) means that, unless the ltc3706 starts and supports the ltc3725 gate drive through the pulse trans- former and on-chip rectifier, the ltc3725 eventually suf- fers a gate drive undervoltage fault. finally, the ltc3706 has an independent overvoltage detection circuit that crowbars the output of the dc/dc converter using the synchronous secondary-side mosfet switch. in the event that a short-circuit is applied to the output of the converter prior to start-up, the ltc3706 generally does not receive enough bias voltage to operate. in this case, the ltc3725 detects a fault for one of two reasons: 1) since the ltc3706 never sends pulse encoding to the ltc3725, the linear regulator times out resulting in a gate drive undervoltage fault, or 2) the primary-side overcurrent circuit is tripped because of current buildup in the output inductor. in either case, the ltc3725 initiates a shutdown followed by a soft-start retry. linear regulator timeout after start-up, the ltc3725 times out the linear regulator to prevent overheating of the external nmos. the timeout interval is set by further charging the soft-start capacitor c ssflt from the end-of-soft-start voltage of approximately 2.8v to the timeout threshold of 3.9v. linear regulator timeout behaves differently depending on mode. in primary-side standalone mode, the ltc3725 generally requires that an auxiliary gate drive bias supply take over from the linear regulator. (see the subsequent section for more detail on the auxiliary supply.) during linear regula- tor timeout, the rate of rise of the soft-start capacitor voltage depends on the current into the ndrv pin as controlled by the pull-up resistor r pullup , the value of v in and the value of v ndrv . i vv r ndrv in ndrv pullup = the value of v ndrv is v cc = 8v plus the value of the gate- to-source voltage (v ndrv ?v cc ) of the external nmos in the linear regulator. the gate-to-source voltage depends on the actual device but is approximately the threshold voltage of the external nmos. for i ndrv > 0.27ma, the capacitor on the ssflt pin is charged in proportion to (i ndrv ?0.27ma) until the linear regulator times out. thus, since v ndrv is very nearly constant, the timeout interval for the linear regulator is inversely proportional to the input voltage and a higher input voltage produces a shorter timeout. t cvv vv r ma timeout ssflt in ndrv pullup = ? ? ? ? ? ? ? 66 39 28 027 (. . ) ? applicatio s i for atio wu uu
ltc3725 13 3725fa applicatio s i for atio wu uu since the power dissipation of the linear regulator is proportional to the input voltage, this strategy of making the timeout inversely proportional to the input voltage produces an approximately constant temperature excur- sion for the external nmos of the linear regulator regard- less of the input voltage. in situations for which the continuous operation of the linear regulator does not exceed the thermal limitations of the external nmos (i.e. converters with low v in or with minimal gate drive bias requirements), the auxiliary sup- ply can be omitted and the linear regulator allowed to operate continuously. if i ndrv is less than 0.27ma the linear regulator never times out and the voltage on the ssflt pin stays at approximately 2.8v after start-up is completed. to accomplish this set: r vv ma pullup in max ndrv > () . 027 where v in(max) is the maximum expected continuous input voltage. note that once the linear regulator is turned off it locks out. therefore when using this strategy, care should be taken to ensure that a transient higher than v in(max) does not persist longer than t timeout . in secondary-side operation with the ltc3706, there is never any need for continuous operation of the linear regulator since gate drive bias power is provided by the ltc3706 through the pulse transformer and on-chip rectifier. the ltc3725 shuts down the linear regulator once the ltc3706 begins switching the pulse trans- former. if the ltc3706 fails to start, the ltc3725 quickly times out the linear regulator once the voltage on the ssflt pin reaches 2.8v. fault lockout the ltc3725 indicates a fault by pulling the ssflt pin to within 1v of v cc . the ltc3725 subsequently attempts a restart. optionally, the user can prevent restart and ?ock out?the converter by clamping the voltage on the ssflt pin with a 4.3v zener diode. once the converter has locked out it can only be restarted by the removal of the input voltage or by release of the zener diode clamp. pulse transformer the pulse transformer that connects the ltc3706 to the ltc3725 performs the dual functions of gate drive duty cycle encoding and gate drive bias supply for the ltc3725 by way of the on-chip full-wave rectifier. the designs of the ltc3725 and ltc3706 have been coordinated so that the transformer turn ratio is: n ltc3725 = 2n ltc3706 where n ltc3725 is the number of turns in the winding connected to the fb/in + and fs/in pins of the ltc3725 and n ltc3706 is the number of turns in the winding connected to the pt + and pt pins of the ltc3706. the winding connected to the ltc3706 must be able to with- stand volt-seconds equal to: () vs v f max cc = 2 where v cc is the maximum supply voltage for the ltc3706 and f is the operating frequency of the ltc3706.
ltc3725 14 3725fa former from their corresponding ltc3706. to synchro- nize operation, the ssflt and v cc pins of the master are connected to the corresponding pins of all the slaves. the master is designated by connection of the frequency set resistor to the fs/in pin while this resistor is omitted from the slaves. for the slaves the ndrv pin is connected to the v cc pin. see the following section on polyphase applica- tions for more detail. polyphase applications figure 4 shows the basic connections for using the ltc3725 and ltc3706 in polyphase applications. one of the phases is always identified as the ?aster,? while all other phases are ?laves.?for the ltc3725 (primary side), the master performs the open-loop start-up and supplies the initial v cc voltage for the master and all slaves. the ltc3725 slaves are put into that mode by omitting the resistor on fs/in? the ltc3725 slaves simply stand by and wait for pwm signals from their respective pulse transformers. since the ssflt pins of master and slave ltc3725s are interconnected, a fault (overcurrent, etc.) on any one of the phases will perform a shutdown/restart on all phases together. for the ltc3706, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the i th pins. faults and shutdowns are communicated via the interconnection of the run/ss pins. the ltc3706 is put into slave mode by tying the fb pin to v cc . auxiliary supply when used with the ltc3706, the ltc3725 does not require an auxiliary supply to provide primary-side gate- drive bias current. after start-up, primary-side gate drive current is provided by the ltc3706 through a small pulse transformer and the ltc3725? on-chip rectifier. however, when used as a standalone primary-side con- troller, the ltc3725 may require a conventional gate-drive bias supply as shown in figure 3. the bias supply must be designed to keep the voltage on the v cc pin between the absolute maximum of 15v and the gate-drive undervoltage lockout of 7v. the auxiliary supply is connected in parallel with v cc . the linear regulator maintains v cc at 8v. if the auxiliary supply produces more than 8v, it turns off the external nmos before the ltc3725 can time out the linear regulator. if the auxiliary supply produces less than 8v, the linear regulator times out and then the voltage on the v cc pin declines to the voltage produced by the auxiliary supply. slave mode operation when the ltc3725 is paired with the ltc3706, multiple pairs can be used to form a polyphase converter. in polyphase operation, one ltc3725 becomes the ?aster while the remainder become ?laves.?the master con- trols start-up in the same manner as for the single-phase converter, while the slaves do not begin switching until receiving pwm information through their own pulse trans- applicatio s i for atio wu uu figure. 3. auxiliary supply for primary-side control power transformer 2.2 f primary winding n p secondary winding n s bas21 bas21 1mh v in ltc3725 3725 f03 ndrv v cc gnd auxiliary winding n a
ltc3725 15 3725fa applicatio s i for atio wu uu figure 4. connections for polyphase ndrv uvlo ltc3725 (master) v cc ss/flt fb/in + fs/in v in v in + v in ndrv v cc pt + pt run/ss ltc3706 (master) ith 3725 f04 v out + v bias fb fs/sync ndrv ss/flt ltc3725 (slave) v cc uvlo fb/in + fs/in v in ndrv v cc pt + pt run/ss ltc3706 (slave) ith fb phase fs/sync standalone primary-side operation the ltc3725 can be used to implement a standalone forward converter using optoisolator feedback and a secondary-side voltage reference. alternately the ltc3725 can be used to implement an open-loop forward converter using the v slmt pin to regulate against changes in v in . in either case, the ltc3725 oscillator determines the fre- quency as found from: f r osc fs p = + 21 10 4200 9 () note that polyphase operation is not possible in the stand- alone configuration. grounding considerations the lt3725 is typically used in high current converter designs that involve substantial switching transients. fig- ure 5 illustrates these currents. the switch driver on the ic is designed to drive a large capacitance and, as such, generate significant transient currents. careful consider- ation must be made regarding input and local power supply bypassing to avoid corrupting the ground refer- ences used by the uvlo and frequency set circuitry. typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from gnd. by virtue of the topologies used in lt3725 applications, the large currents from the primary switch, as well as the switch drive transients, pass through the sense resistor to ground. this defines the ground connec- tion of the sense resistor as the reference point for both gnd and pgnd.
ltc3725 16 3725fa figure 5. high current transient return paths applicatio s i for atio wu uu ltc3725 fs/in gnd signal ground plane power ground plane v in v in gate v cc v cc pgnd uvlo 3725 f05 effective grounding can be achieved by considering the return current paths from the sense resistor to each respective bypass capacitor. don? be tempted to run small traces to separate the grounds. a power ground plane is important as always in high power converters, but care must be taken to keep high current paths away from the gnd reference. an effective approach is to use a 2-layer ground plane, reserving an entire layer for gnd and an entire layer for pgnd. the uvlo and frequency set resistors can then be directly connected to the gnd plane.
ltc3725 17 3725fa typical applicatio s u figure 6. 36v-72v to 3.3v/30a isolated forward converter using ltc3706 efficiency fb/in + 470pf 1 f 100v 2 1 f 100v v in + v in 100 ? 2.2nf 200v 2.2nf 50v 2.2nf 50v 10 f 100 f 6.3v 2 220 f 6.3v v out + 3.3v 30a v out 47nf 470pf 33nf b0540w si7450dp 33nf 470pf 1 f, 100v tdk c3225x7r2a105m (1210) 100 f, 6.3v tdk c3225x5r0j107m (1210) 220 f, 6.3v sanyo 6tpe220m 2.2nf, 250v ac murata ga343qr7gd222kw01l (1210) l1: coilcraft do1813p-331hc l2: pulse pa1294.910 t1: pulse pa0815 6:6:2:1 t2: pulse pa0297 2(1.4mh):1:1 15k 1 f 0.1 f 1 f 2.2nf 250v v out 68pf 2.2 f 5.1k 0.0012 1w hat2165 2 hat2165 2 l2 0.85 h 100 ? 0.030 ? 1w 5.1 ? 1/2w 5.1 ? 1/2w 680pf 1 t2 8 4 3 5 6 100 ? 162k 100 ? 3.3k 100k 2.74k 604 ? 3725 f06a 1.2 ? 1/4w 100k fs/in v cc uvlo ssflt i s gate ltc3725 ndrv gnd pgnd vslmt 365k fdc2512 5 3 4 2 9 7 11 10 t1 23.4 20.1 9.4mm planar pt + fg sw i s i s + sg v in v cc mode ndrv gnd pgnd run/ss slp regsd fs/sync i th phase fcx491a pt fb ltc3706 l1 0.33 h 36v to 72v + load current (a) 5 efficiency (%) 90 48v 72v 36v 92 94 25 3725 f06b 88 86 84 10 15 20 30
ltc3725 18 3725fa typical applicatio s u figure 7. 12v in to 48v/1.5a isolated forward converter using optoisolator fb/in + 10 f 25v 10 f 25v v in + v in 33nf 470pf moc207 105k 470pf 10 f, 25v tdk c3225x7r1e106m (1210) 27 f, 100v sanyo mv-ax 1.5 f, 63v film wima mks2 2.2nf, 250v ac murata ga343qr7gd222kw01l l1: pulse pe-53911 l2, l3: tdk slf12575t-101m1r9 t1: pulse pa0700 3t(16 h):11:11 15k 115k 1 f 100 ? 0.010 ? 1.5w 1nf 100v 100pf 1kv l2 100 h 1nf 2.2nf 250v ac 110 ? 0.5w 27 f 100v l1 1.5mh 1k 3710 4 9.1v 10nf 10nf 100v 2.4k 0.25w 1k 2.4k 0.25w 6 1k 1k 2.49k 8 1 5 6 45.3k 4 5 6 1 2 3 8 1 2 52 1 9611 fs/in v cc uvlo ssflt i s gate ltc3725 ndrv gnd pgnd vslmt mmbd914 mmbd914 t1 efd25 12v 10 f 25v si7370dp 2 l3 100 h ? s ? s 10 9 7 12 murhb860ct + 27 f 100v 1.5 f 63v film v out + v out + gnd-f gnd-s v + lt1431 coll ref 47nf 48v 1.5a
ltc3725 19 3725fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u mse package 10-lead plastic msop (reference ltc dwg # 05-08-1663) msop (mse) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004)
ltc3725 20 3725fa part number description comments ltc1693 high speed single/dual n-channel mosfet drivers cmos compatible input, v cc range: 4.5v to 12v ltc1698 secondary synchronous rectifier controller use with the lt1681, optocoupler driver, pulse transformer synchronization lt1950 single switch controller used for 20w to 500w forward converters ltc3705 2-switch forward controller and gate driver 2-switch version of ltc3725 ltc3706 polyphase secondary-side synchronous fast transient response, self-starting architecture, current mode control forward controller lt3710 secondary-side synchronous post regulator for regulated auxiliary output in isolated dc/dc converters ltc3726 secondary-side synchronous forward controller similar to the ltc3706 lt3781 ?ootstrap?start dual transistor synchronous 72v operation, synchronous switch output forward controller lt3804 secondary side dual output controller regulates two secondary outputs, optocoupler feedback driver with opto driver and second output synchronous driver controller ltc3901 secondary-side synchronous driver for similar function to ltc3900, used in full-bridge and push-pull converter push-pull and full-bridge converter linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1006 rev a ?printed in usa related parts

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